A semiconductor memory device is disclosed. More particularly, an improved semiconductor memory device is disclosed which can generate an internal clock signal synchronized with an external clock signal at rising and falling edges of the external clock signal to thereby perform a high frequency test operation on a wafer level of the device. The problems caused by a high-speed data input/output operations can be exactly detected during a test operation on the wafer level of the device.
Typically, in a wafer level, a semiconductor memory device fabricated through a unit process is put into a test operation of a wafer level to check the device for defects over its memory cell array regions. If a defective cell is found, it is repaired with a spare memory cell provided in the device. In addition to the wafer level test, the semiconductor memory device encapsulated by a package process, which takes place after the fabrication steps at the wafer level, is further inspected for the detects in package level testing. Devices that pass both levels of testing are referred to as verified devices that are considered to be complete memory device chips that are salable.
During a test operation in the package level, a high frequency test can be performed because of a short distance of interface for communicating between test equipment and a semiconductor memory device. However, because interface conditions in a wafer level are not as satisfactorily convenient as those of the package level, it is difficult to conduct a high frequency test operation that substantially coincides with clock signals controlling the test operation. Such mal-coincidence between the test clock signals and the interface performance for test causes propagation skew of operation times as well as a limit for the high frequency test operation. Accordingly, there is a functional limit for the test operations that may be performed at the wafer level because only a basic checkout operation for defects of memory cells can be performed. High frequency test operation is not practical at the wafer level.
Due to the functional limitations involved in the high frequency test operation at the wafer level, a defect not detected during the wafer level test, that is, in a low frequency operation test, is occasionally found in the package level test. In the worst case, the defect may prevent the memory device from being sold, thereby degrading yield.
A practical instance relevant to the aforementioned problems may be illustrated in a synchronous dynamic random access memory (SDRAM). Though SDRAM is usually operated at a frequency of 30 megahertz (MHz) to 60 MHz in a test mode, it is possible for the SDRAM to be used in practical operation at a frequency of more than 100 MHz in a memory system.
The SDRAM reads and writes data at every clock cycle, and thereafter is precharged. Here, if an internal clock signal is provided therein with a low frequency, a normal precharge operation can be carried out with good performance because of a long clock cycle time. On the other hand, if an internal clock signal is introduced therein with a high frequency, a mal-operation may occur in sense amplifiers or memory cells due to the short period of the high frequency clock signal.
Such problems arise because the high frequency test operation cannot harmonize with an internal clock signal made by an internal clock generator receiving an external clock signal having the same frequency as that of the internal clock signal.
Referring to FIG. 1, an internal clock generator 10 includes a clock conversion circuit 12, a buffer 14 transmitting an external clock signal XCLK to the clock conversion circuit 12, and a buffer 16 generating an internal clock signal by inverting and amplifying an output of the clock conversion circuit 12.
The internal clock generator 10 is designed to generate an internal clock signal having a phase or duty cycle that is converted without changing of frequency of the external clock signal XCLK. The internal clock signal generated by the internal clock generator 10 is provided to each element, e.g., a command input buffer 18, requiring the internal clock signal.
In response to the internal clock signal having the same frequency as that of the external clock signal XCLK, the command input buffer 18 buffers a command signal such as a row address strobe signal (RAS) provided from an external source, and then provides the buffered command signal to a command decoder 20. The command decoder 20 decodes a plurality command signals, and generates an active signal ATV.
As described above, in the conventional semiconductor memory device, command signals are buffered or decoded by an internal clock signal having the same frequency with that of the external clock signal XCLK. As a result, the conventional semiconductor memory device is not able to operate properly with the high frequency condition in a wafer level test, and testing at the wafer level is confined to a low frequency test operation.
That is, in the conventional semiconductor memory device, defects of memory cells themselves can be detected, but defects associated with high frequencies such as problems in data input/output performance cannot be found through the wafer level test. Therefore, conventional semiconductor memory devices may have many defects involved in characteristics of the high-speed operation in the package level test that were not found at wafer level testing, which results in yield degradation.
A semiconductor memory device according to this disclosure may process internal command signals, addresses, and data input/output by using an internal clock signal is constructed to generate an internal clock signal synchronized with the external clock signal at its rising and falling edges, resulting in performing a high-speed operation. To this end, a clock generator may include a logic combination circuit for providing a non-inverted and an inverted external clock signal as a first signal and a second signal, respectively, in a test mode. The clock generator may also include a first clock generator for generating a first clock signal synchronized with the external clock signal at its rising edges as the first signal, a second clock generator for generating a second clock signal synchronized with the external clock signal at its falling edges as the second signal, and a logic combination circuit for generating an internal clock signal by receiving the first and the second clock signals. Therefore, in a test mode, the internal clock signal is synchronized with the external clock signal at its rising and the falling edges, and is generated to have a frequency higher than that of the external clock signal, using the internal clock signal to perform a high frequency wafer level test.
The semiconductor memory device may further include a first frequency divider for dividing the internal clock signal into a first divided clock signal synchronized with the external clock signal at its rising edges, and a second frequency divider for dividing the internal clock signal into a second divided clock signal synchronized with the external clock signal at its falling edges.
A data input buffer may include a first switch circuit for temporarily storing an inputted data in response to the first divided clock signal, a second switch circuit for switching the data temporarily stored in the first switch circuit in response to the second divided clock signal, and a latch circuit for receiving the data provided from the first and the second switch circuits, and for temporarily storing the data.
A data output buffer may include a third switch circuit for switching a data that is provided in response to the first divided clock signal, a first output circuit for temporarily storing the data in response to the second divided clock signal, a second output circuit for temporarily storing an output from the third switch circuit and the first output circuit, and a driving circuit for generating data from an output of the second output circuit.